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	<title>Template:Hardware acceleration - Revision history</title>
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	<updated>2026-04-19T03:06:52Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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		<id>http://wiki.filipefonseca.pt/index.php?title=Template:Hardware_acceleration&amp;diff=7812&amp;oldid=prev</id>
		<title>FilipeFonseca: 1 revision imported</title>
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		<updated>2021-07-11T12:23:32Z</updated>

		<summary type="html">&lt;p&gt;1 revision imported&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;{{Navbox&lt;br /&gt;
| name      = Hardware acceleration&lt;br /&gt;
| title     = [[Hardware acceleration]]&lt;br /&gt;
| listclass = hlist&lt;br /&gt;
| state     = {{{state|autocollapse}}}&lt;br /&gt;
&lt;br /&gt;
| group1 = [[Models of computation|Theory]]&lt;br /&gt;
| list1 =&lt;br /&gt;
* [[Universal Turing machine]]&lt;br /&gt;
* [[Parallel computing]]&lt;br /&gt;
* [[Distributed computing]]&lt;br /&gt;
&lt;br /&gt;
| group2 = Applications&lt;br /&gt;
| list2 =&lt;br /&gt;
* [[Graphics processing unit|GPU]]&lt;br /&gt;
** [[General-purpose computing on graphics processing units|GPGPU]]&lt;br /&gt;
** [[DirectX Video Acceleration|DirectX]]&lt;br /&gt;
* [[Sound card|Audio]]&lt;br /&gt;
* [[Digital signal processor|Digital signal processing]]&lt;br /&gt;
* [[Hardware random number generator|Hardware random number generation]]&lt;br /&gt;
* [[AI accelerator|Artificial intelligence]]&lt;br /&gt;
* [[Cryptographic accelerator|Cryptography]]&lt;br /&gt;
** [[TLS acceleration|TLS]]&lt;br /&gt;
* [[Vision processing unit|Machine vision]]&lt;br /&gt;
* [[Custom hardware attack]]&lt;br /&gt;
** [[scrypt]]&lt;br /&gt;
* [[Network processor|Networking]]&lt;br /&gt;
* [[Data processing unit|Data]]&lt;br /&gt;
&lt;br /&gt;
| group3 = Implementations&lt;br /&gt;
| list3 =&lt;br /&gt;
* [[High-level synthesis]]&lt;br /&gt;
** [[C to HDL]]&lt;br /&gt;
* [[Field-programmable gate array|FPGA]]&lt;br /&gt;
* [[Application-specific integrated circuit|ASIC]]&lt;br /&gt;
* [[Complex programmable logic device|CPLD]]&lt;br /&gt;
* [[System on a chip]]&lt;br /&gt;
** [[Network on a chip]]&lt;br /&gt;
&lt;br /&gt;
| group4 = [[Computer architecture|Architecture]]s&lt;br /&gt;
| list4 =&lt;br /&gt;
* [[Dataflow architecture|Data flow]]&lt;br /&gt;
* [[Transport triggered architecture|Transport triggered]]&lt;br /&gt;
* [[Multicore]]&lt;br /&gt;
* [[Manycore]]&lt;br /&gt;
* [[Heterogeneous computing|Heterogeneous]]&lt;br /&gt;
* [[In-memory processing|In-memory computing]]&lt;br /&gt;
* [[Systolic array]]&lt;br /&gt;
* [[Neuromorphic engineering|Neuromorphic]]&lt;br /&gt;
&lt;br /&gt;
| group5 = Related&lt;br /&gt;
| list5 =&lt;br /&gt;
* [[Programmable logic]]&lt;br /&gt;
* [[Processor (computing)|Processor]]&lt;br /&gt;
** [[Processor design|design]]&lt;br /&gt;
** [[Microprocessor chronology|chronology]]&lt;br /&gt;
* [[Digital electronics]]&lt;br /&gt;
* [[Virtualization]]&lt;br /&gt;
** [[Hardware emulation]]&lt;br /&gt;
* [[Logic synthesis]]&lt;br /&gt;
* [[Embedded system]]s&lt;br /&gt;
}}&amp;lt;noinclude&amp;gt;&lt;br /&gt;
{{documentation}}&lt;br /&gt;
[[Category:Computer hardware navigational boxes]]&lt;br /&gt;
&amp;lt;/noinclude&amp;gt;&lt;/div&gt;</summary>
		<author><name>FilipeFonseca</name></author>
	</entry>
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