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{{Navbox
| name = Processor technologies
| title = [[Processor (computing)|Processor technologies]]
| listclass = hlist
| state = {{{state|autocollapse}}}

| group1 = [[Model of computation|Model]]s
| list1 =
* [[Abstract machine]]
* [[Stored-program computer]]
* [[Finite-state machine]]
** [[Finite state machine with datapath|with datapath]]
** [[Hierarchical state machine|Hierarchical]]
** [[Deterministic finite automaton]]
** [[Queue automaton]]
** [[Cellular automaton]]
** [[Quantum cellular automaton]]
* [[Turing machine]]
** [[Alternating Turing machine]]
** [[Universal Turing machine|Universal]]
** [[Post–Turing machine|Post–Turing]]
** [[Quantum Turing machine|Quantum]]
** [[Nondeterministic Turing machine]]
** [[Probabilistic Turing machine]]
** [[Hypercomputation]]
** [[Zeno machine]]
* [[History_of_general-purpose_CPUs#Belt_machine_architecture|Belt machine]]
* [[Stack machine]]
* [[Finite-state machine]]
** [[Finite state machine with datapath|with datapath]]
** [[Hierarchical state machine|Hierarchical]]
** [[Queue automaton]]
* [[Register machine]]s
** [[Counter machine|Counter]]
** [[Pointer machine|Pointer]]
** [[Random-access machine|Random-access]]
** [[Random-access stored-program machine|Random-access stored program]]
| group2 = [[Computer architecture|Architecture]]
| list2 =
* [[Microarchitecture]]
* [[Von Neumann architecture|Von Neumann]]
* [[Harvard architecture|Harvard]]
** [[Modified Harvard architecture|modified]]
* [[Dataflow architecture|Dataflow]]
* [[Transport triggered architecture|Transport-triggered]]
* [[Cellular architecture|Cellular]]
* [[Endianness]]
* [[Computer data storage|Memory access]]
** [[Non-uniform memory access|NUMA]]
** [[Heterogenous Unified Memory Access|HUMA]]
** [[Load/store architecture|Load/store]]
** [[Register–memory architecture|Register/memory]]
* [[Cache hierarchy]]
* [[Memory hierarchy]]
** [[Virtual memory]]
** [[Secondary storage]]
* [[Heterogeneous System Architecture|Heterogeneous]]
* [[Fabric computing|Fabric]]
* [[Multiprocessing]]
* [[Cognitive computing|Cognitive]]
* [[Neuromorphic engineering|Neuromorphic]]

| group3 = [[Instruction set architecture|Instruction set architecture]]s
| list3 =
{{Navbox|subgroup
| group1 = Types
| list1 =
* [[Orthogonal instruction set]]
* [[Complex instruction set computer|CISC]]
* [[Reduced instruction set computer|RISC]]
* [[Application-specific instruction set processor|Application-specific]]
* [[Explicit data graph execution|EDGE]]
** [[TRIPS architecture|TRIPS]]
* [[Very long instruction word|VLIW]]
** [[Explicitly parallel instruction computing|EPIC]]
* [[Minimal instruction set computer|MISC]]
* [[One instruction set computer|OISC]]
* [[No instruction set computing|NISC]]
* [[Zero instruction set computer|ZISC]]
* [[VISC architecture]]
* [[Quantum computing]]
* [[Comparison of instruction set architectures|Comparison]]
** [[Addressing mode]]s
| group2 = Instruction sets
| list2 =
* [[Motorola 68000 series]]
* [[VAX]]
* [[PDP-11 architecture|PDP-11]]
* [[x86]]
* [[ARM architecture|ARM]]
* [[Stanford MIPS]]
* [[MIPS architecture|MIPS]]
* [[MIPS-X]]
* Power
** [[IBM POWER instruction set architecture|POWER]]
** [[PowerPC]]
** [[Power ISA]]
* [[Clipper architecture]]
* [[SPARC]]
* [[SuperH]]
* [[DEC Alpha]]
* [[ETRAX CRIS]]
* [[M32R]]
* [[Unicore]]
* [[IA-64|Itanium]]
* [[OpenRISC]]
* [[RISC-V]]
* [[MicroBlaze]]
* [[Little man computer|LMC]]
* System/3x0
** [[IBM System/360 architecture|S/360]]
** [[IBM System/370|S/370]]
** [[IBM System/390|S/390]]
** [[z/Architecture]]
* [[Tilera ISA]]
* [[VISC architecture]]
* [[Adapteva#Products|Epiphany architecture]]
* [[List of instruction sets|Other]]s
}}

| group4 = [[Instruction cycle|Execution]]
| list4 =
{{Navbox|subgroup
| group1 = [[Instruction pipelining]]
| list1 =
* [[Pipeline stall]]
* [[Operand forwarding]]
* [[Classic RISC pipeline]]
| group2 = [[Hazard (computer architecture)|Hazard]]s
| list2 =
* [[Data dependency]]
* [[Structural hazard|Structural]]
* [[Control hazard|Control]]
* [[False sharing]]
| group3 = [[Out-of-order execution|Out-of-order]]
| list3 =
* [[Scoreboarding]]
* [[Tomasulo algorithm]]
** [[Reservation station]]
** [[Re-order buffer]]
* [[Register renaming]]
* [[Wide-issue]]
| group4 = [[Speculative execution|Speculative]]
| list4 =
* [[Branch predictor|Branch prediction]]
* [[Memory dependence prediction]]
}}

| group5 = [[Parallel computing|Parallelism]]
| list5 =
{{Navbox|subgroup
| group1 = Level
| list1 =
* [[Bit-level parallelism|Bit]]
** [[Bit-serial architecture|Bit-serial]]
** [[Word (computer architecture)|Word]]
* [[Instruction-level parallelism|Instruction]]
* [[Instruction pipelining|Pipelining]]
** [[Scalar processor|Scalar]]
** [[Superscalar processor|Superscalar]]
* [[Task parallelism|Task]]
** [[Thread (computing)|Thread]]
** [[Process (computing)|Process]]
* [[Data parallelism|Data]]
** [[Vector processor|Vector]]
* [[Memory-level parallelism|Memory]]
* [[Distributed architecture|Distributed]]

| group2 = [[Multithreading (computer architecture)|Multithreading]]
| list2 =
* [[Temporal multithreading|Temporal]]
* [[Simultaneous multithreading|Simultaneous]]
** [[Hyper-threading|Hyperthreading]]
* [[Speculative multithreading|Speculative]]
* [[Preemption (computing)|Preemptive]]
* [[Cooperative multitasking|Cooperative]]

| group3 = [[Flynn's taxonomy]]
| list3 =
* [[SISD]]
* [[SIMD]]
** [[Single instruction, multiple threads|Array Processing (SIMT)]]
** [[Flynn's taxonomy#Pipelined_Processor|Pipelined Processing]]
** [[Flynn's taxonomy#Associative_Processor|Associative Processing]]
** [[SWAR]]
* [[MISD]]
* [[MIMD]]
** [[SPMD]]
}}

| group6 = [[Computer performance|Processor performance]]
| list6 =
* [[Transistor count]]
* [[Instructions per cycle]] (IPC)
** [[Cycles per instruction]] (CPI)
* [[Instructions per second]] (IPS)
* [[FLOPS|Floating-point operations per second]] (FLOPS)
* [[Transactions per second]] (TPS)
* [[SUPS|Synaptic updates per second]] (SUPS)
* [[Performance per watt]] (PPW)
* [[Cache performance measurement and metric|Cache performance metrics]]
* [[Computer performance by orders of magnitude]]

| group7 = [[Processor (computing)|Types]]
| list7 =
* [[Central processing unit]] (CPU)
* [[Graphics processing unit]] (GPU)
** [[General-purpose computing on graphics processing units|GPGPU]]
* [[Vector processor|Vector]]
* [[Barrel processor|Barrel]]
* [[Stream processing|Stream]]
* [[Tile processor]]
* [[Coprocessor]]
* [[Programmable Array Logic|PAL]]
* [[Application-specific integrated circuit|ASIC]]
* [[Field-programmable gate array|FPGA]]
* [[Field-programmable object array|FPOA]]
* [[Complex programmable logic device|CPLD]]
* [[Multi-chip module]] (MCM)
* [[System in package]] (SiP)
* [[Package on a package]] (PoP)
{{Navbox|subgroup
| group1 = By application
| list1 =
* [[Embedded processor]]
* [[Microprocessor]]
* [[Microcontroller]]
* [[Mobile processor|Mobile]]
* [[Notebook processor|Notebook]]
* [[Ultra-low-voltage processor|Ultra-low-voltage]]
* [[Application-specific instruction set processor|ASIP]]
* [[Soft microprocessor]]
| group2 = Systems on chip
| list2 =
* [[System on a chip]] (SoC)
* [[Multiprocessor system on a chip|Multiprocessor]] (MPSoC)
* [[Cypress PSoC|Programmable]] (PSoC)
* [[Network on a chip]] (NoC)
| group3 = [[Hardware acceleration|Hardware accelerators]]
| list3 =
* [[Coprocessor]]
* [[AI accelerator]]
* [[Graphics processing unit]] (GPU)
* [[Image processor]]
* [[Vision processing unit]] (VPU)
* [[Physics processing unit]] (PPU)
* [[Digital signal processor]] (DSP)
* [[Tensor processing unit]] (TPU)
* [[Secure cryptoprocessor]]
* [[Network processor]]
* [[Baseband processor]]
}}

| group8 = [[Word (computer architecture)|Word size]]
| list8 =
* [[1-bit computing|1-bit]]
* [[4-bit computing|4-bit]]
* [[8-bit computing|8-bit]]
* [[12-bit computing|12-bit]]
* [[Apollo Guidance Computer|15-bit]]
* [[16-bit computing|16-bit]]
* [[24-bit computing|24-bit]]
* [[32-bit computing|32-bit]]
* [[48-bit computing|48-bit]]
* [[64-bit computing|64-bit]]
* [[128-bit computing|128-bit]]
* [[256-bit computing|256-bit]]
* [[512-bit computing|512-bit]]
* [[bit slicing]]
* [[Word (computer architecture)#Table of word sizes|others]]
** [[Word (computer architecture)#Variable word architectures|variable]]

| group9 = Core count
| list9 =
* [[Single-core]]
* [[Multi-core processor|Multi-core]]
* [[Manycore processor|Manycore]]
* [[Heterogeneous computing|Heterogeneous architecture]]

| group10 = Components
| list10 =
* [[Processor core|Core]]
* [[Cache (computing)|Cache]]
** [[CPU cache]]
** [[Scratchpad memory]]
** [[Data cache]]
** [[Instruction cache]]
** [[Cache replacement policies|replacement policies]]
** [[Cache coherence|coherence]]
* [[Bus (computing)|Bus]]
* [[Clock rate]]
* [[Clock signal]]
* [[FIFO (computing and electronics)|FIFO]]
{{Navbox|subgroup
| group1 = [[Execution unit|Functional unit]]s
| list1 =
* [[Arithmetic logic unit]] (ALU)
* [[Address generation unit]] (AGU)
* [[Floating-point unit]] (FPU)
* [[Memory management unit]] (MMU)
** [[Load–store unit]]
** [[Translation lookaside buffer]] (TLB)
* [[Branch predictor]]
* [[Branch target predictor]]
*[[Memory controller|Integrated memory controller]] (IMC)
**[[Memory management unit]]
* [[Instruction decoder]]
| group2 = [[Digital logic|Logic]]
| list2 =
* [[Combinational logic|Combinational]]
* [[Sequential logic|Sequential]]
* [[Glue logic|Glue]]
* [[Logic gate]]
** [[Quantum logic gate|Quantum]]
** [[Gate array|Array]]
| group3 = [[Hardware register|Register]]s
| list3 =
* [[Processor register]]
* [[Status register]]
* [[Stack register]]
* [[Register file]]
* [[Memory buffer register|Memory buffer]]
* [[Memory address register]]
* [[Program counter]]
| group4 = [[Control unit]]
| list4 =
*[[Hardwired control unit]]
* [[Instruction unit]]
* [[Data buffer]]
* [[Write buffer]]
* [[Microcode]] [[ROM image|ROM]]
* [[Microcode#Horizontal microcode|Horizontal microcode]]
* [[Counter (digital)|Counter]]
| group5 = [[Datapath]]
| list5 =
* [[Multiplexer]]
* [[Demultiplexer]]
* [[Adder (electronics)|Adder]]
* [[Binary multiplier|Multiplier]]
** [[CPU multiplier|CPU]]
* [[Binary decoder]]
** [[Address decoder]]
** [[Sum addressed decoder]]
* [[Barrel shifter]]
| group6 = [[Electronic circuit|Circuitry]]
| list6=
* [[Integrated circuit]]
** [[Three-dimensional integrated circuit|3D]]
** [[Mixed-signal integrated circuit|Mixed-signal]]
** [[Power management integrated circuit|Power management]]
* [[Boolean circuit|Boolean]]
* [[Digital circuit|Digital]]
* [[Analog circuit|Analog]]
* [[Quantum circuit|Quantum]]
* [[Switch#Electronic switches|Switch]]
}}

| group11 = [[Power management|Power management]]
| list11 =
* [[Power Management Unit|PMU]]
* [[Advanced Power Management|APM]]
* [[Advanced Configuration and Power Interface|ACPI]]
* [[Dynamic frequency scaling]]
* [[Dynamic voltage scaling]]
* [[Clock gating]]
* [[Performance per watt]] (PPW)
* [[Race to sleep]]

| group12 = Related
| list12 =
* [[History of general-purpose CPUs]]
* [[Microprocessor chronology]]
* [[Processor design]]
* [[Digital electronics]]
* [[Hardware security module]]
* [[Semiconductor device fabrication]]
* [[Tick–tock model]]
* [[Pin grid array]]
* [[Chip carrier]]

}}<noinclude>{{documentation}}</noinclude>

Template:Processor technologies - Revision history

FilipeFonseca: 1 revision imported